The present invention generally relates to spread spectrum signal processing, and more particularly to arrangements for de-spreading spread spectrum signals.
Code Division Multiple Access (CDMA) is a rapidly expanding data transmission technique and lies at the heart of the Universal Mobile Telecommunications System (UMTS), which is presently in development in many countries. CDMA transmits data over a wide bandwidth and separates the users of that bandwidth by coding each signal with a unique code sequence.
Generally, one part of a spread spectrum system involves breaking a data bit into multiple sub-bits or xe2x80x9cchipsxe2x80x9d. For example, the signal is multiplied by a Pseudo-random Noise (PN) code, which is a sequence of values of amplitude +1 and xe2x88x921 which are commonly be represented by the logical levels of xe2x80x980xe2x80x99 and xe2x80x981xe2x80x99 respectively. To de-spread a received signal, input samples are multiplied by the same PN code, which effectively cancels the original coding.
A single time slot matched filter (STSMF) is used in a spread spectrum system to perform the multiplication operations in the receiver. The products generated each chip period are accumulated for a data period and used to indicate whether a valid data bit has been received and if so, the value of the data bit. Conventional STSMF designs for programmable logic devices, such as FPGAs consume a large portion of programmable resources available on a device, thereby making FPGA solutions relatively expensive. For multi-finger applications, the resource consumption is compounded by virtue of the multiple STSMFs and associated control and result collection logic.
The mobility of transmitters and receivers in spread spectrum systems introduces transmission path delay that must be addressed in de-spreading a signal. Over-sampling is one technique that is useful in de-spreading signals in mobile systems. However, the higher the over-sampling rate the greater the computational requirements of the de-spreader. Further complicating matters, when the transmission path delay exceeds a chip period, the timing of the code sequence must be adjusted so that the code sequence and signal are in phase. Present de-spreader techniques consume considerable resources if implemented on an FPGA.
An apparatus and method that address the aforementioned problems, as well as other related problems, for FPGAs and other types of electronic devices are therefore desirable.
A correlation circuit arrangement for de-spreading spread spectrum signals is presented in various embodiments. In one embodiment, the correlation circuit arrangement includes an adder-subtractor and a shift register arrangement. The adder-subtractor adds an input sample value to or subtracts the sample value from an accumulated correlation value, responsive to an input PN code. The adder-subtractor is time-multiplexed between one or more PN code generators and correlation values are accumulated in the shift register arrangement. In another embodiment, transmission path delay can be analyzed by using the shift register arrangement to store correlation values that result from delaying the PN code across multiple chip periods. In other embodiments, the adder-subtractor and shift register arrangement are in various combinations implemented with function generators of a programmable logic device.
It will be appreciated that various other embodiments are set forth in the Detailed Description and Claims that follow.